Lead Digital Verification Engineer

page_title Back to jobs Lead Digital Verification Engineer San Jose, CA OR Pittsburgh, PA OR Austin, TX Apply Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution We are looking for an experienced Design Verification Lead to drive the functional verification of complex SoC/IP designs from specification through tapeout in a newly formed hardware engineering organization. You will own the verification strategy, define methodology standards, build and guide a team of verification engineers, and serve as the final authority on verification quality and sign-off readiness. This role demands a strong blend of technical depth in modern verification methodologies (UVM, embedded C and compiler generated trace driven testing) and the leadership ability to execute across a multi-block chip program on schedul.e The DV Lead will help shape our internal processes for building robust and verified designs, including the company’s second product line, which will scale computing performance and capability, while improving energy efficiency. This is a unique opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond! Key

Responsibilities Define the end-to-end verification strategy across block, subsystem, and full-chip levels aligned with tapeout milestones Author and review verification plans mapping specifications to features, stimulus strategies(traditional stimulus generation, compiler driven), coverage goals, and sign-off criteria Architect scalable UVM-based testbench environments including agents, scoreboards, reference models, and coverage monitors Drive constrained-random stimulus development targeting protocol interactions, concurrency, error injection, and corner cases Define and close functional coverage models through systematic hole analysis, targeted tests, seed optimization, and regression tuning Deploy SystemVerilog Assertions for protocol compliance, interface checks, and design invariants across all simulation runs Lead full-chip verification including boot sequences, interrupt handling, DMA flows, power-on reset, and multi-block interactions Ensure CDC, RDC, and multi-power-domain verification in coordination with specialist tools and teams Debug complex simulation failures spanning multi-block interactions, protocol violations, race conditions, and timing-dependent corner cases Own the bug lifecycle — triage, prioritization, tracking, fix verification, and cross-functional resolution with RTL designers and architects Manage the regression framework — defining suites, maintaining stability, optimizing throughput, and integrating with CI/CD pipelines Coordinate simulation-to-emulation handoff ensuring verification collateral transitions effectively to emulation environments Collaborate cross-functionally with Compiler Team, RTL design, DFT, physical design, and post-silicon validation teams Lead, mentor, and grow the verification engineering team while maintaining a high quality bar through rigorous reviews Represent verification readiness in tapeout sign-off reviews and program-level decisions Support running gate-level simulations as part of design signoff. Assist in building a verification dashboard to quickly understand where a design is in the verification process and to identify regressions. Required