About the role
Position: Sr. Engineer, Analog/Mixed-Signal Modelling and Verification Location: Bengaluru, India Job Id: 693 # of Openings: 0 Senior Engineer, Analog/Mixed Signal Modelling and Verification Location: Bengaluru (on-site, hours flexible) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. We are seeking an experienced Senior AMS Modelling and Verification Engineer, to join our Silicon Engineering team. In this senior role, you will contribute to the behavioral modelling and verification of complex, high-performance integrated circuits, with a primary focus on custom analog, mixed-signal, and/or high-speed digital blocks. The ideal candidate has experience in mixed signal modelling and verification flows for mixed signals IPs such as PLLs, serdes, etc. Key
Responsibilities Understand the
requirements and functionality of assigned mixed signal blocks. Develop test plans for mixed signal blocks. Work with the analog designers and
the team lead to understand the schematic and capture the most important parameters of the circuits in system verilog RNM, and their first and second order effects. Develop a behavioral model for the mixed signal block in terms of signal processing components using system verilog RNM Develop model vs schematic comparison using Cadence or Synopsys tool flows. Provide continuous feedback to
the team lead on model vs schematic mismatches. Verify and sign-off on mixed signal RNM models for the assigned blocks. Help the SoC verification team in integrating the critical mixed signal IP into the full chip digital environment. Basic
