Sr. Staff Engineer, ASIC Design

Position: Sr. Staff Engineer, ASIC Design Location: Bengaluru, India Job Id: 593 # of Openings: 0 Sr. Staff Engineer, ASIC Design Location: Bangalore (on-site, flexible hours) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. The ASIC Sr. Staff Engineer is responsible for the design, bring-up, and debug of complex digital subsystems within an electro-optical digital SoC. You will work in a dynamic startup environment as part of a small IC design team, with each team member expected to contribute across a broad range of tasks while gaining new skill sets to grow with the company. The ideal candidate is a hands-on self-starter who can craft specifications based on input from colleagues, customers, and industry and who can effectively manage his or her own time to take projects to completion with limited supervision and guidance. KEY

RESPONSIBILITIES: Develop detailed digital algorithm specifications in collaboration with analog, photonics, and firmware engineers Develop and optimize RTL in verilog for use in complex electro-optical ASICs Develop models and testbenches for digital and mixed-signal blocks Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation (clocks and timing constraints, floorplan guidance, testability) and collaborate to ensure timing signoff Bringup, evaluation, and debug of in-house custom silicon using python scripting, firmware, and control systems Contribute to automated design methodologies and flows for ASIC digital design Hands-on work with high-speed interconnects and optical systems Required

Qualifications: BS or MS in Electrical Engineering, Computer Engineering, or related fields 5+ years of work or academic experience in ASIC design History of assuming responsibility for a variety of technical tasks and completing projects independently Mastery of Verilog and SystemVerilog for both RTL design and verification Proficient in ASIC verification (XCelium, VCS, Questa) tools Proficient in low-level programming languages (C, C++) Proficient in Python Working knowledge of digital timing constraints and ASIC tool flows Experience working on digital designs with multiple clock domains and clock dividers Experience with SOC interconnect fabrics (AMBA AXI/AHB/APB) Preferred