About the role
Position: Principal Engineer, Analog/Mixed-Signal Modelling and Verification Location: Bengaluru, India Job Id: 694 # of Openings: 0 Principal Engineer, Analog/Mixed Signal Modelling and Verification Location: Bengaluru (on-site, hours flexible) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. We are seeking an exceptionally skilled and experienced Principal AMS Modelling and Verification Engineer, to join our Silicon Engineering team. In this senior role, you will own the behavioral modelling and verification of complex, high-performance integrated circuits, with a primary focus on custom analog, mixed-signal, and/or high-speed digital blocks. The ideal candidate is a recognized expert in mixed signal modelling and verification flows with experience of leading multiple silicon proven mixed signals SoCs with critical components such as PLLs, serdes on the advanced semiconductor nodes. Key
Responsibilities Lead the mixed signal verification for Ayar Labs mixed signal SoCs. Mentor the AMS Verification team members. Work with architects to understand the
requirements and functionality of mixed signal blocks. Independently develop test plans for mixed signal blocks. Work with the analog designers to understand the schematic and capture the most important parameters of the circuits in system verilog RNM, and their first and second order effects. Understand the functional
requirements for mixed signal components and develop a behavioral model in terms of signal processing components using system verilog RNM Develop model vs schematic comparison using Cadence or Synopsys tool flows. Verify and sign-off on mixed signal RNM models . Help the SoC verification team in integrating the critical mixed signal IP into the full chip digital environment. Own and maintain these models through the lifecycle of the product. Basic
