About the role
Job Details: Job Description:
The Role and Impact As a Physical Design Engineer, you will play a pivotal role in the implementation of custom IP and SoC designs, ensuring they are optimized for manufacturing and performance. Your day-to-day
responsibilities will involve executing the physical design flow from RTL to GDS, including synthesis, place and route, timing analysis, and verification. By bringing your expertise to this critical part of chip design, you'll contribute to delivering high-performance, reliable, and innovative products that drive Intel's technological advancements. Business group You will be joining Intel's cutting-edge design engineering team, which focuses on creating world-class solutions for silicon design and manufacturing. The group collaborates across domains to develop advanced methodologies that support Intel's mission to produce high-performing, energy-efficient, and scalable products. With a culture rooted in innovation and teamwork, the group plays a key role in shaping Intel's leadership in semiconductor technology. Key
Responsibilities - Conduct end-to-end physical design implementation of custom IP and SoC designs from RTL to GDS. - Execute synthesis, floor planning, place and route, and clock tree synthesis to meet design specifications. - Perform static timing analysis, noise glitch/signal integrity analysis, and power distribution optimization. - Analyze verification results, including equivalence checks, power integrity, reliability checks, and timing closure, and make recommendations for resolving violations. - Collaborate with cross-functional teams to optimize design parameters such as power, area, and frequency. - Contribute to the development and enhancement of physical design methodologies, flows, and automation for improved efficiency and scalability.
Qualifications: Minimum
Qualifications - Bachelor's degree in a specialized field such as Electrical Engineering, Computer Engineering, or similar with 8+ years of hands-on experience in physical design OR Master's degree with 6+ years of experience OR PhD with 4+ years of experience. - Proficiency in key physical design tools and flows, including synthesis, FC / Innovus place and route, static timing analysis, and verification methodologies. - Expertise in design optimization techniques, power planning, clock tree synthesis, and low-power design methodologies. - Demonstrated ability to handle EDA tools with the latest AI/ML capabilities for design automation. - Strong scripting skills for flow automation and process efficiency (e.g., Python, Perl, TCL). Preferred