About the role
Position: Sr. Staff Engineer, Analog/Mixed-Signal Design Location: San Jose, CA Job Id: 591 # of Openings: 0 Sr. Staff Engineer, Analog/Mixed-Signal Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. As an Analog and Mixed Signal Design Engineer, you will design various blocks such as oscillators, high speed transmitters/receivers, biasing circuits, linear regulators, ADCs/DACs, and others. You will work as a part of a small IC design team in a dynamic startup environment. The ideal candidate is a hands-on self-starter who is able to develop design specifications based on input from colleagues, customers, and industry and who can effectively manage his or her own time to take projects to completion with limited supervision and guidance. Key
Responsibilities: Architect and design high speed signal path for high bandwidth optical links Work closely with optical and digital design teams to architect mixed-signal control loops Design analog/mixed signal circuits such as oscillators, high speed transmitters/receivers, amplifiers, biasing circuits, linear regulators, ADCs/DACs, and others Define, run, and automate sign-off verification simulations Create design review and testing documentation Perform post-silicon bring-up of circuits in lab Required
Qualifications: M.S. in Electrical Engineering 6+ years of work experience in analog/mixed signal design Experience designing high speed analog blocks such as PLLs, clock distribution and multi-phase generation, high swing transmit drivers, high speed receive analog front ends. Proficient with Cadence design environment and mixed-signal simulation (ADE, Layout, Spectre) Have experience designing in FinFet CMOS (7nm or below) at data rates of at least 50Gb/s and/or RF circuits operating at 25GHz or above Preferred
