Senior Principal Engineer – Hardware Chip Lead, Connectivity BU

requirements — are complete and on schedule Mentorship & Knowledge Sharing · Mentor and develop engineers across the ODSP hardware organization; invest in building technical depth and breadth within

the team · Foster a culture of knowledge sharing, technical rigor, and continuous learning · Coach and develop engineering talent; provide guidance and feedback to support career growth at all levels

What We're Looking For Education & Experience · Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field and 15+ years of related professional experience · OR Master’s degree in Electrical Engineering, Computer Engineering, or related field with 10–12 years of experience · OR PhD in Electrical Engineering, Computer Engineering, or related field with 8–10 years of experience Required Skills & Experience · Proven track record as a chip lead or equivalent technical owner on complex SoC/ASIC programs, from architecture through tape-out and post-silicon productization · Deep expertise in high-speed mixed-signal SoC design, including SerDes (100G+/lane), DSP datapath, analog/digital integration, and advanced CMOS process nodes (5nm, 3nm) · Strong understanding of the full ASIC design flow: micro-architecture, RTL, synthesis, DFT, physical design, STA, timing closure, and tape-out · Experience leading and coordinating cross-functional hardware teams across analog, digital, DV, DFT, PD, firmware, validation, and test engineering disciplines · Demonstrated ability to drive silicon bring-up, debug, and validation across multi-site global teams · Experience with ATE test program development, silicon characterization, qualification (HTOL, ESD, LU), and production release · Excellent communication, interpersonal, and presentation skills; ability to represent hardware engineering to BU leadership and cross-functional stakeholders · Highly motivated, self-driven, and able to manage ambiguity in a fast-paced, multi-program environment Preferred Skills · Familiarity with optical DSP, coherent or direct-detect transceiver architectures, or high-speed retimer products · Experience with eAVS (Adaptive Voltage Scaling) or similar power optimization subsystems · Knowledge of SiPho (Silicon Photonics) integration and module-level validation · Experience working in a multi-site, globally distributed engineering organization Expected Base Pay Range (USD) 182,360 - 273,200, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience,

qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional

Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive

benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected]. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-TT1 Join our talent community to hear about company news, job openings and events. Join our Talent Community! Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Recruitment fraud is a well-known way that third parties try to get personal information or to steal money from you. Please review Marvell’s guidance here to learn more on how you can protect yourself.

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