Digital Verification Engineer | Aviva Links Skip to content Aviva Links is now a part of NXP Semiconductors®, accelerating asymmetrical ASA multi-gigabit connectivity in SDVs. Read full story Main Menu Technology Applications Products About News Main Menu Technology Applications Products About News Careers Digital Verification Engineer About Aviva Links Aviva Links is a leading startup founded by industry veterans with a solid track record of technology innovation and business execution. We are building advanced connectivity solutions for next generation autonomous systems utilizing our deep domain expertise in multi-gigabit technologies. If you are passionate about developing cutting-edge technologies and building successful products with high impact, we want to talk to you. Job Location Pune, Bengaluru, India (Full Time) Job Description Summary We are developing state-of-the-art SoCs from architecture to final product involving automotive centric design methodologies and flows tailored for functional safety. We have a presence across multiple geographies and are currently in search of a Principal level IP/SoC Design Verification Engineer.
RESPONSIBILITIES Develop testbenches using System Verilog and UVM for functional and power aware RTL Develop UVM component like agents (active and passive), scoreboards and environment etc., Develop assertions, functional coverage. Develop test plan, UVM based test sequences, layered sequences, virtual sequencers Drive closure of verification metrics to cover verification space. Work with
the team to identify and close gaps in functional, power aware and Gate level timing simulation. Develop ‘C’ testcases for HW-FW simulation and FPGA prototyping Provide regression setup, debug of RTL and gate level netlist Review industry standard spec and augment test plan to improve quality of verification Participate in post silicon bring up, validation and compliance testing and debug Work collaboratively with cross-functional teams like ASIC Architect, ASIC Designers, firmware development team to ensure successful delivery of product MINIMUM
QUALIFICATIONS Proven track record of verification, taking several chips from specification to tape out Proven expertise with UVM and/or System Verilog based verification Excellent understanding of ASIC verification methodologies and proven experience of verification Experience working with source control tools, bug management tools and release management tools such as Jenkins, Git, and Jira. Experience with SoC interfaces, embedded processors, networking protocols, security protocols and video formats will be a big plus. Strong written and verbal communication skills and ability to work independently. Bachelors in Electrical Engineering or equivalent and 5+ years of experience Apply for the Digital Verification Engineer Position " * " indicates required fields Email This field is for validation purposes and should be left unchanged. Your Name * Your Email * Phone * Message * Attach Your Resume * Max. file size: 50 MB. Attach Another File Max. file size: 50 MB. CAPTCHA Aviva Links is now a part of NXP Semiconductors®, accelerating asymmetrical ASA multi-gigabit connectivity in SDVs. Read full story Main Menu Technology Applications Products About News Linkedin-in Twitter Copyright © 2026 Aviva Links - All Rights Reserved. Privacy Policy Scroll to Top
Location
Bengaluru Area, Pune Area
Experience
5+ years
Total raised
$33.0M
Last stage
Series A
Investors
No applications, no recruiter spam. Just the intro.
A few questions to make sure this role is the right shape for you. Two minutes.
I write the intro, send it to the founder, and handle the back-and-forth.
If they’re a yes, I book the chat. You show up — that’s the whole job-hunt.