About the role
Position: Principal Engineer, Digital Verification and Emulation Location: San Jose, CA Job Id: 584 # of Openings: 0 Principal Engineer, Digital Verification & Emulation Location: San Jose, CA — on-site Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics, or CPO, we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry leaders including NVIDIA, AMD, MediaTek and Intel, and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to enabling next-generation AI scale-up architectures. We are seeking a Principal Engineer, Digital Verification & Emulation to lead verification and hardware-assisted validation for our next-generation silicon photonic chip. This role will focus on digital verification, emulation bring-up, mixed-signal-aware verification, real-number modeling, and software-driven pre-silicon validation. This is a senior individual-contributor technical leadership role working closely with architecture, RTL design, analog/mixed-signal, firmware, software, systems, and validation teams. Essential Functions Lead hardware-assisted verification using emulation platforms such as Synopsys ZeBu, Cadence Palladium, Siemens Veloce, or equivalent. Own emulator bring-up, compile/debug flows, model mapping, debug visibility, runtime optimization, and emulation regression execution. Build reusable verification environments for complex IP blocks, subsystems, and SoC-level designs using SystemVerilog, checkers, monitors, scoreboards, transactors, memory models, bus-functional models, and emulation-ready test infrastructure. Adapt simulation environments for emulation and acceleration, including synthesizable components, test migration, and emulator-friendly verification methodology. Develop, integrate, and validate real-number models, behavioral models, and mixed-signal abstraction models for analog/digital interface verification. Partner with firmware and software teams to run pre-silicon workloads, diagnostics, register tests, traffic generation, and long-running system scenarios on emulation platforms. Collaborate with architects and RTL designers to define verification plans, identify design risks, improve testability, and ensure readiness for simulation, emulation, and tape-out. Debug complex failures across RTL, verification infrastructure, emulation models, firmware, embedded software, and mixed-signal behavioral models. Define and track functional coverage, code coverage, assertions, verification metrics, exclusions, waivers, and signoff criteria. Use assertions and formal techniques selectively for control logic, interfaces, reset behavior, CDC/RDC-sensitive logic, and difficult corner cases. Develop scripts, flows, dashboards, and automation for regressions, emulation builds, job scheduling, log analysis, performance tracking, and coverage reporting. Mentor engineers, conduct technical reviews, and drive verification methodology across
