About the role
About the Company Omni Design Technologies provides high-performance, ultra-low power IP solutions across advanced CMOS nodes, enabling differentiated SoC architectures for AI/ML accelerators, hyperscale datacenter interconnects, optical networks, and next-generation wireline platforms. We partner with market leaders globally and are scaling rapidly, and are seeking senior technical leadership to define the next generation of ultra high-speed SerDes IP at 448G and beyond. Job Description We are seeking a Principal / Lead DSP & Systems Architect to own the architectural direction of ultra high-speed SerDes platforms targeting 448G per lane and emerging post-448G standards, spanning both electrical (chip-to-chip, backplane, copper cable) and optical (IM-DD and coherent) interfaces. This individual will drive end-to-end link architecture, DSP algorithm design, and ADC/DAC-based transceiver partitioning, serving as the primary technical interface with strategic customers and standards bodies. The ideal candidate combines deep expertise in high-speed link theory, advanced equalization and FEC, PAM/multi-level and coherent signaling, and hardware-aware DSP implementation, with a track record of delivering SerDes IP into silicon at the bleeding edge of the wireline and optical roadmap. \n Key
Responsibilities Architecture & Roadmap: Define DSP and system architecture for 448G and post-448G SerDes IP across electrical and optical interfaces — including ADC/DAC-based transceiver partitioning, modulation choice (PAM4/PAM6, IM-DD, coherent), and FEC strategy — and shape long-term roadmap toward 1.6T and 3.2T link aggregates. Customer & Standards Engagement: Lead technical engagement with hyperscale, AI accelerator, and optical module customers; represent the company in OIF CEI, IEEE 802.3, and related standards activities. End-to-End Link Modeling: Build and maintain MATLAB/Python models of the full link across electrical and optical media: channel response (backplane, copper cable, chip-to-chip, fiber), TX/RX impairments, jitter (RJ/DJ/BUJ), crosstalk, reflections, optical impairments (CD, PMD, laser phase noise, optical SNR), ADC/DAC quantization, and FEC performance under realistic BER/FLR targets. DSP Algorithm Architecture: Own the DSP pipeline across electrical and optical paths — FFE, DFE, MLSE/MLSD, CTLE-DSP partitioning, adaptive equalization (LMS, sign-sign LMS, blind adaptation), timing recovery and CDR, baseline wander correction, IQ/skew calibration, PAM demapping, and integration with KP4 / concatenated / soft-decision FEC. For optical links, additionally drive chromatic dispersion (CD)
