About the role
Job Details: Job Description: Intel's HIPD team is looking for an experienced senior Logic design engineer to join the rapidly growing UCIE PHY IP for Intel's flagship datacenter/server designs.
Responsibilities will include but not limited to: - Develops the logic design, register transfer level (RTL) coding, and simulation for IP block. - Participates in the definition of architecture and microarchitecture features of the block being designed. - Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. - Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. - Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Behavior skills we are looking for: - Excellent written and oral presentation skills, and willing to work across multiple organizations and geographies. - Effective team player with continuous learning mindset. - Strong analytical and problem-solving skills. - Be willing to balance multiple tasks. - Ramp quickly on new and complex IPs in a dynamic environment is critical.
Qualifications: You must possess the below minimum
qualifications to be initially considered for this position. Preferred
qualifications are in addition to the minimum
requirements and are considered a plus factor in identifying top candidates. Minimum
Qualifications: Candidate must possess a Bachelor's degree in Electrical or Computer Engineering or a related field and 4+ years' experience OR a Master's degree in Electrical or Computer Engineering or a related field and 2+ years' experience OR a PhD in Electrical or Computer Engineering or a related field and 1+ years' experience. Relevant Work Experience must be in: RTL/Logic design using System Verilog Language Experience with Design of Data path, Power-management flow, Arbitration logic, Clock Domain Crossing, State Machines, UPF Experience with Front End design tools for Lint, Synthesis. Experience with hardware simulation tools and methodologies (VCS/Verdi). Familiarity with IP environment and configuration management tools. Preferred