About the role
We are looking for a Design Verification Engineer with 10–15 years of experience to join Architect as one of a small but growing team of DV experts helping verify AI-generated chip designs taping out on leading foundries. You'll be a critical voice at the intersection of rigorous hardware verification and cutting-edge AI-driven design automation — directly shaping how AI systems verify chips in the future. We're a fast-moving, 18-person startup (Stanford spin-out, $23M seed) working with chip companies to co-design ASICs, and our designs are going into high-volume production on TSMC technology. If you've verified AI accelerators, NPUs, or inference ASICs end-to-end and want to be at the forefront of both AI and silicon, this is your seat.
What will you be doing?
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Own and drive functional verification of AI-generated ASIC designs — from block-level IP through SoC integration — targeting real tape-outs on leading process nodes.
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Define and execute UVM-based verification environments, coverage models, microarchitectural checkers, and test plans for internal and customer chip programs.
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Provide deep DV domain expertise to AI/ML teams, encoding best practices into AI-driven verification flows and helping build the next generation of automated DV tooling.
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Collaborate cross-functionally with architecture, design, and AI/ML leads to develop simulation- and emulation-ready collateral that scales across multiple concurrent projects.
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Bring startup urgency to aggressive tape-out timelines — we have a test chip targeting December and need people who move faster than the schedule, not with it.
