Principal Engineer, Design for Test (DFT)

Position: Principal Engineer, Design for Test (DFT) Location: Bengaluru, India Job Id: 600 # of Openings: 0 Principal Engineer, Design for Test (DFT) Location: Bengaluru, India (On-site, flexible hours) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry leaders and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solutions are enabling next-generation AI scale-up architectures. The Principal DFT Engineer will lead Design-for-Test architecture, implementation, and silicon bring-up for complex electro-optical SoCs and chiplet-based systems. This role requires strong technical leadership across scan architecture, ATPG, MBIST/LBIST, silicon debug, and production test methodologies. You will work closely with ASIC Design, AMS, Photonics, Physical Design, Validation, Firmware, and Product Engineering teams to deliver high-quality silicon with strong manufacturability, test coverage, and production readiness. The ideal candidate is a hands-on technical leader who thrives in a fast-paced startup environment and can drive DFT execution from architecture definition through production ramp. KEY

RESPONSIBILITIES Define and drive SoC-level DFT architecture and implementation strategy for advanced ASIC and electro-optical SoCs Lead scan insertion, ATPG generation, MBIST/LBIST integration, JTAG/boundary scan, and compression methodologies Develop and validate DFT constraints, timing

requirements, and test modes in collaboration with RTL and Physical Design teams Drive fault coverage closure, pattern validation, and silicon test debug activities Collaborate with ASIC, AMS, Packaging, Firmware, Validation, and Product Engineering teams to ensure successful silicon bring-up and production readiness Support post-silicon validation, characterization, yield analysis, and manufacturing ramp activities Develop automated methodologies, flows, and infrastructure to improve DFT quality and execution efficiency Drive root-cause analysis for silicon test failures and manufacturing issues Work closely with EDA vendors and external partners on DFT tool flows and methodologies Mentor engineers and provide technical leadership across DFT and related domains REQUIRED