About the role
At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI.
About
the Role As the Senior Staff SI/PI Engineer, you will be the technical authority responsible for the electrical integrity of d-Matrix’s high-performance AI compute platforms. In an environment where we are pushing 112G/224G SerDes and delivering thousands of Amps to multi-chip modules (MCM), your role is critical to ensuring that our "Digital In-Memory Computing" architecture translates into stable, manufacturable, and world-class hardware. You will lead the end-to-end modeling, simulation, and correlation efforts—from the silicon die through the package and across the system PCBA. Key
Responsibilities • End-to-End SI/PI Ownership: Drive the SI/PI strategy for next-generation AI accelerators, focusing on high-speed interfaces (PCIe Gen6/7, CXL, LPDDR5) and custom Chiplet-to-Chiplet interconnects. • MCM & Package Simulation: Lead the modeling and analysis of complex multi-chip packages, including interposer routing, micro-bump parasitic extraction, and die-to-die (D2D) link budgeting. • Advanced PDN Architecting: Design and optimize the Power Delivery Network (PDN) to meet stringent Z_Target
requirements. Perform transient analysis to ensure voltage stability during massive AI workload swings. • Link Analysis & Budgeting: Perform comprehensive channel simulations (pre- and post-layout) using IBIS-AMI models. Define jitter, crosstalk, and loss budgets (insertion/return loss) for 112G+ channels. • Lab Correlation & Measurement: Lead the "Gold Suite" validation in the lab. Correlate simulation results with VNA, TDR, and high-speed oscilloscope measurements to close the loop on design accuracy. • Constraint Management: Translate complex simulation findings into actionable physical layout constraints for the PCB Design team, specifically for advanced stack-ups and high-density routing. • Technical Mentorship: Act as the subject matter expert, guiding hardware and layout engineers on SI/PI best practices and state-of-the-art mitigation techniques (e.g., skip-vias, voiding, material selection). Required
