About the role
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, and networking applications. What You Can Expect As a full chip STA engineer , you will be responsible for running/supporting/maintaining the Global Timing Flow using industry standard EDA tools for designing the next generation Multi-Ghz high-performance processor SOC chips in leading-edge CMOS process technology. Experienced in IP constraint development and integration, constraint management and pushdown, ECO flows is a must. Work with design teams across various disciplines such as Digital/RTL/Analog/DFT in helping them take their blocks (custom, PnR) through the global timing flow and making sure all the blocks meet timing
requirements. Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes. Writing scripts in TCL and Perl to achieve productivity enhancements through automation
What We're Looking For BSEE or MS with 12 to 25 years of experience running an industry standard EDA tool for global timing is required (PrimeTime preferred). Experience in tape-outs of high-performance SOC is highly desired. Understanding of several timing-related concepts is required: setup, hold, clocking, timing corners, timing constraints, noise, and process variation. Knowledge of scripting languages such as Perl/TCL is required. Diligent, detail-oriented, and handle assignments with minimal supervision. Must possess good communication skills, self-driven individual and a good team player. Additional