About the role
Company Overview Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions. Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications. Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology. We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency. At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve. If that's you, join us — the intelligence everywhere revolution starts here. Build the silicon that powers the future of ultra-low-power computing At Ambiq, we’re redefining what’s possible at the edge—powering next-generation AI, wearables, and IoT devices with breakthrough ultra-low-power technology. We’re looking for a Sr. Staff Engineer – Timing Methodology to take a true ownership role in driving timing from architecture to silicon—and ensuring our designs don’t just work, but excel in real-world conditions. Why this role stands out This isn’t a “maintain the flow” role. You’ll: Own end-to-end timing convergence (block → SoC → post-silicon) Shape methodology, flows, and signoff strategy Work on cutting-edge FinFET, multi-patterning nodes , and unique ultra-low-power challenges Directly influence PPA and product success If you thrive on solving complex timing problems others shy away from—this is your playground. What You’ll Do Own timing convergence end-to-end , from methodology definition to SoC signoff Develop and refine timing flows, constraints, and analysis methodologies Drive block-level closure and SoC-level timing correlation Lead signoff activities , including: PVTR corner definition Timing margining & ECO strategy Extraction and analysis Glitch/noise analysis & power/timing tradeoffs Partner cross-functionally with RTL, DFT, physical design, and IP teams Define and manage timing constraints across diverse IP (std cell, memory, hard IP) Ensure strong pre-silicon to post-silicon correlation through close collaboration with bring-up and validation teams Continuously enhance automation, scripts, and methodologies to improve efficiency and scalability Stay at the forefront of STA advancements and emerging process technologies What You Bring 8+ years of experience in timing analysis and convergence Deep expertise in static timing analysis (STA) using Synopsys Primetime or Cadence Tempus Strong experience with block-level and SoC-level timing closure in advanced nodes Solid understanding of digital design fundamentals and timing principles Hands-on experience with industry-standard EDA tools (Synopsys, Cadence) Proficiency in TCL, Python, or similar scripting languages Strong problem-solving skills and ability to drive complex issues to closure Excellent communication and collaboration skills across engineering teams
