About the role
Drive physical implementation of custom SRAM, Register File (RF), cache, and memory layouts in advanced process technologies, including floorplanning, hierarchy development, placement, routing, and physical integration. Collaborate with circuit design, architecture, physical design, CAD, foundry, and SoC teams to optimize memory IP for power, performance, area (PPA), reliability, manufacturability, and integration readiness. Perform physical verification and signoff activities including DRC, LVS, ERC, antenna, density, EMIR, reliability analysis, debug, and closure support. Deliver production-ready memory IP collateral, including GDS/OASIS, LEF abstracts, integration views, documentation, and signoff packages for SoC integration. Develop and improve custom memory layout methodologies, design-rule adoption, automation flows, and productivity solutions using SKILL, TCL, or similar scripting languages. Partner with internal engineers, contractors, and external layout teams to review deliverables, resolve technical issues, and support execution to program milestones. Identify technical risks, communicate status and tradeoffs clearly, and support multiple custom memory programs across advanced technology nodes with high-quality execution. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. 5+ years of custom memory layout experience including SRAMs, Register Files, cache structures, embedded memories, or high-density memory architectures. Experience using Cadence Virtuoso and Siemens/Mentor Calibre physical verification tools. Experience with DRC, LVS, ERC, antenna, and physical signoff verification on advanced-node designs. Experience with FinFET and/or Gate-All-Around process technologies. Experience collaborating with circuit design teams to optimize memory IP for power, performance, and area. Experience owning or contributing to custom memory IP deliveries from specification through tapeout, including SRAM, Register File (RF), cache, or related embedded memory architectures. Strong understanding of SRAM and RF architecture fundamentals, including bitcell integration, row/column peripheral circuitry, assist circuitry, redundancy implementation, and layout tradeoffs. Experience supporting memory integration through LEF/abstract generation, timing or physical collateral development, signoff documentation, and SoC integration readiness. Experience with EMIR analysis and reliability signoff using Ansys Totem, Cadence Voltus, or equivalent tools. Strong automation and scripting skills using Python, SKILL, TCL, Perl, or similar languages to improve layout productivity and quality. Experience with advanced technology nodes such as 5nm, 3nm, or beyond, and familiarity with analog/mixed-signal layout considerations. Experience working with geographically distributed teams, contractors, vendors, or design-service partners to deliver layout milestones.
