Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

requirements.Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows BASIC

QUALIFICATIONS: Bachelor’s degree in electrical engineering, computer engineering or computer science 5+ years of ASIC and/or physical design flow development experience in industry PREFERRED SKILLS AND EXPERIENCE: Experience and deep understanding of SOC top level physical design flows (floor-planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation) Experience in IP integration (e.g. memories, I/O’s, analog IPs, SerDes, DDR etc.) Deep expertise in DRC, LVS, PERC and ESD verification methodologies Hands-on proficiency with Calibre, ICV (IC Validator), or Pegasus Direct foundry DRM experience — able to read, interpret, and implement complex rule decks Experience at advanced nodes (4nm and below) Experience with large SOC designs (>10M gates) with frequencies in excess of 1GHZ Excellent scripting skills (csh/bash, Perl, Python TCL, Makefile etc.) Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment ADDITIONAL

REQUIREMENTS: Ability to work extended hours and weekends as needed to meet critical project milestones ITAR

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