About the role
About OLIX AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.
The Role We are seeking an experienced Physical Design Technical leader with a strong focus on AI-enhanced methodology to take a lead role in building our Physical Design team and design environment. This role will be a combination of leading portions of the Physical Design execution along with defining a world-class design environment that leverages modern AI-enhanced design tools/flows. This is a highly collaborative, in-office role based in Austin, TX, working closely with cross- functional teams locally while also partnering with engineers in our London and Bristol offices to drive coordinated, global execution.
Responsibilities An individual in this role will not be expected to cover ALL of the following areas of focus but
the role will be expected to contribute in a range of areas. Provide technical leadership to internal and external PD resources during the design of the OLIX compute die. Assist in the definition of the chip floorplan, partitioning strategy, and hierarchical implementation model across digital and analog boundaries Provide focused leadership to
the team optimizing PPA (power, performance, area) for the different subsystems across the design. Work with the timing engineers to drive the design to final timing closure and power integrity. Provide leadership in enabling AI-based enhancements for the PD design flows. Skills & Experience 12+ years of experience in ASIC physical design, with multiple successful tapeouts Hands-on experience in advanced FinFET nodes (7nm, 5nm, or below) Proven experience leading large-scale physical design efforts across distributed, multi-site, or global teams Strong track record managing external vendors or design service partners Deep expertise in timing closure, power integrity, and physical verification at advanced nodes Strong understanding of full-chip floorplanning, including analog/digital partitioning