About the role
The candidate for this position will be expected and able to complete the following
responsibilities: Responsible for product and engineering activities supporting new product development and manufacturing, with primary focus on scan (structural) test. Contribute to silicon bring-up, validation, and manufacturing readiness while working closely with cross-functional partners. Support semiconductor IC development across fabrication, manufacturing test, and packaging phases. Contribute to ATE test program development, including scan pattern integration, test method implementation, bring-up, silicon characterization, debug, and yield analysis for logic defects. Execute defined test plans and methodologies while identifying issues and escalating risks with clear technical data. Apply working knowledge of Design-for-Test (DFT), including scan architecture, ATPG, fault models, silicon fabrication processes, product qualification and reliability, and basic transistor theory. Collaborate with design, DFT, product, and manufacturing teams to support scan test readiness, coverage closure, and issue resolution. Gain exposure to product domains such as high-performance computing, AI, GPUs, and telecom, as applicable to assigned projects. Apply industry-standard DFT features, including scan (SAF/TDF), JTAG, boundary scan, and at-speed testing. Support scan test content generation, including ATPG pattern validation, pattern bring-up, and post-silicon debug activities. Understand scan fault models (e.g., stuck-at and transition faults), coverage targets, and defect screening methodologies. Utilize scan diagnosis tools to perform failure analysis, identify defect locations, and support yield improvement activities. Work with DFT teams to support simulation, emulation, and pattern verification for scan test validation. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. 5+ years of experience in integrated circuit development, including pre-silicon, first silicon bring-up, or new product introduction. 5+ years of experience in product and test engineering, with hands-on exposure to ATE test program development, bring-up, and debug for scan. Experience working on complex SoCs or chips, including exposure to high-performance, AI, or advanced-node designs. Clear written and verbal communication skills with the ability to present technical data effectively. Experience collaborating with cross-functional teams in a structured development environment. Working knowledge of probability, statistics, and basic DOE concepts. Familiarity with DFT and DFM techniques, with emphasis on scan/structural test methodologies. Experience with scan/ATPG methodologies, including pattern generation, validation, and test flows. Understanding silicon bring-up, debug, and characterization on ATE platforms (e.g., Advantest 93K) for scan test content. Exposure to mixed-signal IP test development and its interaction with structural test is a plus. Basic device physics background. Demonstrated adaptability, curiosity, and constructive problem-solving approach. Strong Growth Mindset with a desire to learn and expand technical depth. Fundamentals of computer architecture. Good unit and integration testing skills. Proficiency with Linux-based environments. Experience debugging and optimizing test programs, ATPG patterns, or validation flows. Customer-focused mindset with attention to quality, coverage, and execution. Demonstrated ability to deliver results on assigned tasks with guidance. Sound technical judgment in scoping and resolving well-defined problems.
