Senior FPGA Engineer, Cyber

requirements into robust FPGA implementations. Drive precision timing, synchronization, and throughput closure for the selected FPGA/SoC platform and adjacent high-speed digital interfaces. Document architectures, interfaces, and verification approaches clearly enough for cross-functional integration and long-term maintainability. Support design reviews, technical trade studies, and lab debugging with a hands-on, player-coach engineering mindset. REQUIRED

QUALIFICATIONS Strong experience with FPGA development on Xilinx or comparable platforms, including SoC/MPSoC-based or other high-performance digital devices relevant to SDR systems. Proficiency in VHDL, Verilog, or SystemVerilog, including simulation, timing closure, and resource/performance tradeoffs. Experience building high-speed digital interfaces and datapaths such as Ethernet-based packet movement, DMA-adjacent flows, or streaming signal pipelines. Hands-on familiarity with precision timing, synchronization, sysref/clocking concepts, and deterministic interface behavior. Experience with FPGA verification methodologies and automation, including regression-oriented testbenches and CI-backed validation. Ability to collaborate effectively with software and DSP engineers on register interfaces, control surfaces, and integration boundaries. Comfort debugging in the lab using oscilloscopes, logic analyzers, spectrum analyzers, or related instrumentation. Strong written and verbal communication skills for technical design reviews and cross-functional engineering work PREFERRED

QUALIFICATIONS Experience with cocotb, GitLab CI/CD, or similar automation for FPGA verification and release confidence. Background in FFT/channelization pipelines, PSD generation, AGC-adjacent blocks, or other signal-processing-oriented FPGA implementations. Familiarity with embedded software interfaces to FPGA systems, including Linux-based control planes and hardware/software co-debug. Experience presenting architecture and implementation details in customer-facing or formal design-review settings. Track record of mentoring other engineers and improving design quality across a broader FPGA/DSP team. US Salary Range $166,000 — $220,000 USD The salary range for this role is an estimate based on a wide range of

compensation factors, inclusive of base salary only. Actual salary offer may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are included in the majority of full time offers; and are considered part of Anduril's total

compensation package. Additionally, Anduril offers top-tier

benefits for full-time employees, including:

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