About the role
Lead RTL/FPGA Design Engineer Lead RTL/FPGA Design Engineer About Aalyria: Aalyria is a leading technology company that supplies laser communications technology and temporospatial software-defined networking platforms to the aerospace industry. With technology acquired from Google, Aalyria is at the forefront of innovation in satellite and airborne mesh networks, as well as cislunar and deep-space communications. We are revolutionizing the orchestration and management of planetary mesh networks using any radio or optical spectrum, any orbit, and any hardware across land, sea, air, and space. Role Overview: As the Lead RTL/FPGA Design Engineer on our Aalyria Space team, you will own the end to end the development of a high-performance coherent modem targeting free space optical (FSO) communications. In this role, you'll own the RTL development of that modem from architecture through silicon bring-up. That means translating complex DSP algorithms, equalization, carrier recovery, timing recovery, into clean, synthesizable RTL, integrating high-throughput FEC engines, and ensuring the full design meets the demanding power, performance, and area targets required for a fielded aerospace system. You'll work directly alongside DSP algorithm developers and system architects, serving as the bridge between mathematical models and working hardware. This is a remote position that will include occasional travel to our Mountain View office location. Key
Responsibilities: Deliver end-to-end FPGA Modem Solution based on VHDL or System Verilog. Lead the micro-architecture and RTL development for key digital signal processing (DSP) blocks in the coherent modem, including equalization, carrier recovery, and timing recovery. Oversee the integration of Forward Error Correction (FEC) engines and high-speed interfaces into the overall modem architecture. Collaborate with system architects and DSP algorithm developers to translate DSP algorithm specification/ models into robust RTL designs. Design fixed-point arithmetic RTL implementation of complex DSP blocks. Ensure the design is compliant with relevant industry or company standards and specifications. Apply low power design techniques and perform power, performance, and area (PPA) analysis. Verify intended functionality using thorough test benches, and via vector matching with system models. Support functional verification, debug, and static timing closure. Collaborate closely with firmware/software engineers to define hardware/software partitioning, define registers and interfaces, and support system-level integration and debug. Support silicon bring-up and bench testing. Required
