Lead RTL Design Engineer

the team. Driving PPA Metrics: Participate in PPA analysis loops: synthesize blocks regularly, review area/timing/power reports, and make data-driven tradeoffs against performance and feature

requirements. DV Collaboration: Collaborate with DV leads to define/review verification plans; provide directed test scenarios for graph execution corner cases, back-pressure conditions, and power state transitions. Silicon Bring-up: Support silicon bring-up: contribute scan/ATPG guidelines, review DFT insertion, and provide RTL-level debug assistance during lab validation. Required

Qualifications & Experience 8+ years of RTL design experience with tape-out ownership of dataflow based design, on chip networks, memory subsystems or peripheral integration on a processor or accelerator SoC. Deep proficiency in SystemVerilog for RTL — synthesis-clean, lint-clean, timing-aware; able to design complex state machines, arbiters, token flow controllers, and datapath logic from scratch. Solid understanding of parallel execution models: dataflow, SIMD, or systolic array architectures; familiarity with the hardware challenges of token-based firing-rule evaluation and producer-consumer synchronization. Hands-on experience with on-chip memory design: SRAM wrappers, scratchpad/TCM, banking, and memory-mapped register interfaces. Experience with low-power RTL techniques: UPF-driven flows, clock gating, power domains, retention registers, and AON wakeup logic. Familiarity with at least one standard on-chip bus protocol (AXI, AHB, APB, TileLink, or NoC equivalent) at the RTL implementation level. Experience taking RTL through synthesis and timing closure; ability to read and act on SDC constraints, STA reports, and synthesis QoR summaries. Strong written communication skills; able to produce uArch specs and design review material independently. Experience with memory compiler toolchains Desired

Qualifications & Experience

Requirements Prior RTL ownership of a dataflow engine, neural processing unit (NPU), or streaming DSP architecture with explicit producer-consumer token management. Experience collaborating with compiler or graph-optimization teams to co-design hardware execution models and graph IR representations. Familiarity with NVM controller RTL (MRAM, RRAM) including ECC, program/erase sequencing, and model weight storage use cases. Experience with IoT-class power budgets (sub-10 mW active, sub-100 µW standby) and the RTL design choices they necessitate. Familiarity with functional safety standards (ISO 26262, IEC 61508) as applied to execution fabric error detection and power domain isolation. Exposure to AI framework graph formats (ONNX, TFLite) and understanding of how graph compilation maps to hardware execution primitives. Tape-out credits on an edge-AI, IoT, or wearable SoC at 12nm or below. Experience with formal verification of flow-control logic, deadlock freedom, or bus protocol compliance. We offer a competitive salary for this role, generally ranging from $160,000 to $250,000, along with meaningful equity and comprehensive

benefits. The final

compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

Why Join Efficient? Efficient offers a competitive

compensation and

benefits package , including 401K match, company-paid

benefits, equity program, paid parental leave, and flexibility . We are committed to personal and professional development and strive to grow together as people and as a company. Create a Job Alert Interested in building your career at Efficient Computer? Get future opportunities sent straight to your email. Create alert Apply for this job * indicates a required field Autofill with MyGreenhouse First Name * Last Name * Preferred First Name Email * Phone Country Phone Resume/CV Attach Attach Dropbox Google Drive Enter manually Enter manually Accepted file types: pdf, doc, docx, txt, rtf Cover Letter Attach Attach Dropbox Google Drive Enter manually Enter manually Accepted file types: pdf, doc, docx, txt, rtf LinkedIn Profile Website Submit application Powered by Greenhouse

A meeting lands on your calendar

If they’re a yes, I book the chat. You show up — that’s the whole job-hunt.