About the role
Position: Director, SoC Design Location: Bengaluru, India Job Id: 592 # of Openings: 0 Director, SoC Design Location: Bengaluru (on-site, flexible hours) At Ayar Labs, we are shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry leaders including NVIDIA, AMD, and Intel, Ayar Labs’ optical interconnect technology is enabling the next generation of AI scale-up architectures. The Director, SoC Design will lead end-to-end SoC integration and execution activities across complex semiconductor programs. This role will drive execution excellence across IP integration, Technical Flow Management (TFM), design quality, milestone readiness, and cross-functional coordination to ensure successful tape-outs and product delivery. The ideal candidate is a strong technical and organizational leader with deep expertise in large-scale SoC integration, execution management, and semiconductor development methodologies. KEY
RESPONSIBILITIES SoC Integration & Execution Lead SoC integration activities across internal IPs, subsystems, and third-party/vendor components. Drive architecture-to-implementation alignment and scalable integration methodologies. Oversee integration readiness, dependency management, interface compatibility, and closure activities. Collaborate closely with Architecture, RTL Design, DV, Physical Design, DFT, Firmware, and Platform teams. IP BOM Management Own and maintain the SoC IP BOM across programs including: IP version tracking Deliverable compliance Dependency management Release alignment Configuration consistency Ensure accurate documentation and traceability of internal and external IP deliverables. Drive governance for IP intake, qualification, signoff, and release processes. Technical Flow Management (TFM) Establish and drive robust TFM processes across SoC programs. Define integration flows, quality gates, handoff criteria, and execution checkpoints. Monitor design health metrics, schedule adherence, and execution risks. Drive continuous improvement in SoC methodologies, automation, and execution efficiency. Quality & Design Governance Lead quality checks and signoff readiness across: RTL quality Lint/CDC/RDC closure Low-power verification Integration sanity Verification readiness Signoff metrics Ensure compliance with organizational design standards and best practices. Drive root-cause analysis and corrective actions for execution issues. Milestone & Program Management Own milestone gate reviews and readiness assessments across major program phases including: Architecture freeze RTL freeze Integration freeze Verification signoff Tapeout readiness Track schedules, dependencies, execution metrics, and risks across teams. Present status, risks, and mitigation plans to senior leadership. Cross-Functional Leadership Lead and mentor technical leads and integration managers. Coordinate execution across global engineering teams and external partners/vendors. Influence roadmap planning, execution strategies, and resource prioritization. REQUIRED
