About the role
Job Application for Physical Design - Timing Lead at Efficient Computer Back to jobs Physical Design - Timing Lead San Jose, CA OR Pittsburgh, PA OR Austin, TX Apply Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution Efficient is seeking a Physical Design - Timing Lead to join our growing team. The Timing Lead will work on timing convergence and methodology hands on for the world’s most energy-efficient, general-purpose processor . This role will be in the newly formed hardware engineering group and will focus on designing in state of the art finfet technologies.
The role is cross functional and we are a integrated highly interdisciplinary team of world class engineers. This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond! Key
Responsibilities Drive and develop Timing flows, methodology for state of the art finfet and multi patterning based technologies from scratch in Cadence Tempus or Synopsys Primetime. Own and drive timing convergence of IP, Subsystem and SOC blocks. Define timing margining, PVTRC corner definitions, extraction methodology , signoff timing to SYN/PNR correlation. Develop slew rate, glitch noise checks to ensure robust design quality. Develop custom timing checks as pertains to Efficients proprietary Ultra low power architecture. Work closely with RTL team, DFT and IP vendors to define and drive SDC constraints. Have an in-depth understanding of all collaterals for all hard and soft IPs used by the design. Partner with post-si products bring up team to ensure good pre-si to post-si correlation from a timing perspective. Work with 3rd party vendor resources and coordinate their work in the timing domain. Continuously work on improving flow consistency and efficiency in the context of multiple product type swim lanes. Required