About the role
About
the Team OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads.
The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure,
the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.
About
the Role We are seeking a highly capable Implementation Engineer & Technologist to drive silicon construction and optimization for next-generation AI chips. This is a senior hands-on individual-contributor role for an engineer who combines strong technical breadth with the ability to go deep quickly, solve hard problems, and land results in collaboration with cross-functional teams. You will operate across architecture, circuits, memory, RTL, physical implementation, and integration technologies to turn amb itious product goals into manufacturable silicon. This role is not limited to analysis or pathfinding—you will be expected to develop solutions, prototype ideas, drive execution, and close critical gaps. The ideal candidate is a hands-on generalist with strong engineering judgment, deep circuit intuition, broad semiconductor knowledge, and a habit of using AI tools to move faster and make better decisions. In this role, you will: Partner with architecture and system teams to translate product goals into executable silicon construction strategies. Drive hands-on optimization of power, performance, area, cost, and reliability across the silicon stack. Develop and implement solutions spanning circuits, memory, RTL, physical design, and integration. Use and build AI-driven tools, flows, and methodologies to accelerate silicon implementation. Evaluate new technologies and convert them into reliable product constructions optimized for performance, performance/TCO, and performance/W. You might thrive in this role if: BS with 12+ years, MS with 10+ years, or PhD with 6+ years of relevant industry experience in chip design or implementation. Strong hands-on expertise in circuits and implementation-driven PPA optimization. Deep knowledge of semiconductor technologies including memory, advanced nodes, packaging, and 3D integration. Hands-on experience with RTL design and physical implementation through tapeout. Proven ability to work across disciplines and solve complex technical problems end-to-end. Strong use of AI tools for engineering productivity, analysis, coding, or design optimization. Excellent technical communication and collaboration skills. Preferred
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