Principal Signal & Power Engineer (Die to Die and Chiplet Design)

The SMPE silicon team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom IP and SoC designs that can perform complex and high-performance functions in an extremely efficient manner. SIPI engineer for compute and AI SoCs and platforms - Implement strategies for end-to-end design and analysis of D2D interfaces, HBM interfaces, system-level interfaces and associated package technology decisions and tradeoffs. Deliver SIPI solutions that meet the HPC demands across the entire system. Drive future SIPI solutions for chiplet architecture with advanced packaging and advanced silicon nodes Design, model, and simulate Signal and Power Integrity effects (i.e., incl. IP design, voltage regulator, motherboard, CPU package, silicon, decoupling capacitor solutions, dielectric and copper loss, high-frequency discontinuities, timing budgets, power supply induced jitter, etc.) for data center processors and corresponding platforms to ensure optimized performance. Performs DC, AC and transient simulation to provide a comprehensive prediction of timing/noise margins, and to validate I/O performance from platform to silicon. Work closely with silicon and platform architects, motherboard and package designers, thermal architects and engineers, and power and performance engineers. Drives the execution of architecture solutions across product lines or multiple product groups across teams that account for design trends and future concepts by leveraging cross- functional expertise, industry best practices, and lessons learned from teams working across multiple product lines Drives engineering system design decisions that require collaboration between internal and external stakeholders to account for platform-specific technology decisions and develop system models based on current and anticipated feature/design needs and trade-offs. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. MSEE degree with 10 years' experience in silicon packaging products development Experience with power integrity modelling for HPC products Foundation in advanced packaging technologies as it relates Power integrity Experience with Foundry Silicon technologies, OSAT technologies and Substrate technologies BSEE degree with minimum 10 years' experience in silicon/package/system power integrity/delivery Foundation in the field of Power Integrity and delivery, System design, IP design with knowledge on product development with minimum 7 years' experience in design and electrical modelling Working knowledge in the field of end to end system SIPI Design and Architecture Industry knowledge, trends and landscape of technologies to drive development across Silicon-IP, Advanced packaging, Substrate technology, Board technology and Platform design