About the role
Position: Principal Engineer, Analog/Mixed-Signal Design Location: San Jose, CA Job Id: 610 # of Openings: 0 Principal Engineer, Analog/Mixed Signal Design Location: San Jose, CA (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. We are the pioneers of co-packaged optics, using light instead of electricity to move data faster, further, and with a fraction of the energy that today's electrical I/O requires. Our optical I/O is what next-generation AI scale-up architectures need to keep growing. We are backed by NVIDIA, AMD, MediaTek and Intel, and we manufacture in partnership with the world's leading semiconductor ecosystem. We are hiring a Principal Analog/Mixed Signal Design Engineer to shape the architecture of our next-generation co-packaged optics product. You will set the AMS direction across our roadmap, help define what gets built next and why, and be the technical authority the rest of the AMS organization works with on the hardest challenges. Key
Responsibilities: Architect the high-speed optical PHY of our next-generation product: TX path, RX path, clocking, and mixed-signal control loops against a system-level link budget shared with the photonics and laser teams. Set the AMS technical direction across our roadmap. Translate system-level specs into AMS subsystem architecture and block specs. Lead the silicon-success methodology: first-silicon-success expectations, debug discipline, characterization-to-production. Mentor AMS design engineers in design reviews and silicon debug. Drive co-design across the EIC/PIC boundary. Represent the AMS organization in cross-functional architecture reviews, customer technical engagements, and foundry/EDA partner discussions. Basic
Qualifications: M.S. or Ph.D in Electrical Engineering 12+ years of industry experience in analog/mixed signal design Track record of production tapeouts in advanced FinFET CMOS nodes Design experience with high speed and high precision analog blocks such as PLLs, clock distribution and multi-phase generation, TX/RX analog front ends, data converters, and references/regulators. Fluent with Cadence design environment and mixed-signal simulation (ADE, Layout, Spectre). Experience driving architectural tradeoff analysis using link budgeting tools. Experience designing in FinFet CMOS (7nm or below) at data rates of at least 50Gb/s and/or RF circuits operating at 25GHz or above. Preferred
