About the role
In this role, you will be responsible to: Own execution from synthesis to place and route of partition through all signoff including timing signoff, physical verification, EMIR signoff, Formal Equivalence, and Low Power Verification. Own partition floor planning for optimizing blocks for Power, Performance and Area. Additionally flow flush PD TFM on few design partitions for early identification of any design PD flow issues before every PD TFM release is proliferated and deployed across all partitions/subchips for PD execution. Partner closely with PD flow/CAD team and PD methodology team to flag & fix PD TFM issues upfront and ensure those are fixed in the next PD TFM release from CAD or are updated in the design project layer (as appropriate). Have close collaboration with RTL team to help drive and resolve design issues related to block closure. Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach. Have good scripting skills in one or more scripting languages (viz., Tcl, Perl). Expertise in Python will be a big plus. BS/BE/BTech/MS/ME/MTech in Electronics or Microelectronics/VLSI, or Electrical Engineering Min 6+ years of experience in semiconductor design. Good communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams. Proven track record of implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification. Large SoC/CPU/IP design tape-out experience in the latest foundry process nodes. Project management skills and ability to juggle multiple projects at once. Good understanding of constraints generation, STA, timing optimization, and timing closure. In-depth understanding of design tradeoffs for power, performance, and area. Hands on experience with CTS techniques such as Htree, custom clock tree, Experience of implementing (VA Planning, secondar PG planning) in multi-voltage, multi-powerdomain, and low power designs. Experience and knowledge of formal equivalency checks, LEC, LP, UPF, reliability, SI, and Noise. Experience in EDA tools such as Fusion Compiler, Primetime, StarRC, RedHawk, Formality, etc. Exposure and some hands-on experience with PD flows bring up/setup/flow flush, overall know how of PD-TFM and PD methodology is a big plus Problem-solving and data analysis skills Automation skills using scripting languages such as Perl, TCL, or Python.
