About the role
Position: Sr. Staff Engineer, Package and Interconnect Reliability Location: San Jose, CA Job Id: 636 # of Openings: 0 Sr. Staff Engineer, Package and Interconnect Reliability Job Location: On-site in San Jose Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Position Summary We are seeking a highly skilled and motivated Staff Package and Interconnect Reliability Engineer to lead the reliability qualification and physics-of-failure analysis for our next-generation silicon photonics products. In this role, you will be the core technical authority ensuring the structural, thermal, and optical alignment integrity of highly complex 3D/2.5D IC packaging architectures. You will work closely with advanced foundry partners (including TSMC) to qualify advanced packaging technologies like COUPE (Compact Optical Engine), micro-bump/hybrid bonding, precision die attach, and critical optical-to-electrical interfaces such as Fiber Array Units (FAUs) and optical connectors. Key
Responsibilities Advanced Packaging & Heterogeneous Integration Reliability Advanced Bonding & Micro-Assembly: Qualify and optimize the reliability of critical wafer-to-wafer and die-to-wafer bonding processes, including Cu-Cu hybrid bonding, micro-bumps, and high-density copper pillars. Precision Die Attach: Establish reliability margins and wear-out mechanisms for high-accuracy sub-micron die attach processes utilized for co-packaging lasers (InP/GaAs) and Electronic Integrated Circuits (EIC) onto the Photonic Integrated Circuit (PIC). Foundry Collaboration: Partner closely with advanced foundries—specifically TSMC—to evaluate, stress-test, and sign off on advanced packaging platforms like COUPE, CoWoS, and InFO variants tailored for optical engines. Optical Interconnect & FAU Reliability Fiber Array Unit (FAU) Integration: Drive reliability qualification for the optical interface, specifically addressing epoxy degradation, glass/silicon sub-mount stability, and the mechanical retention of FAUs over lifetime environmental stressors. Optical Connectors: Own the qualification of next-generation pluggable and co-packaged optical connectors. Evaluate insertion/extraction cycling, dust contamination vulnerabilities, and mating force effects on optical alignment stability. Sub-Micron Alignment Stability: Define test strategies to monitor and mitigate sub-micron sub-component shifting under extreme thermal cycling (TCT), high-temperature storage (HTSL), and biased damp heat testing. Failure Analysis & Physics of Failure (PoF) Root Cause Analysis: Drive deep-dive Failure Analysis (FA) on components that fail during reliability stress testing using advanced techniques (e.g., CSAM, High-resolution X-ray, SEM/EDX, FIB, and optical interferometry). Thermo-Mechanical Modeling Interaction: Collaborate with FEA (Finite Element Analysis) teams to evaluate the impacts of CTE (Coefficient of Thermal Expansion) mismatches between optical elements, substrates, and optical epoxies. Mitigation Strategies: Provide actionable feedback to Design for Excellence (DFX), Package Design, and Process teams to mitigate risks like electromigration, thermo-mechanical fatigue, creep, and interfacial delamination. Required
