Design Verification Engineer

Owns verification of one or more aspects/features of a custom IP/block or IP subsystem integration Learns about the design and interact with partner teams to define verification strategies and test plans Develops UVM-based or Formal verification environments and run and debug simulations to drive quality Applies random-stimulus and coverage-based techniques to find bugs and meet test plan goals Innovates to improve verification efficiency through methodologies or tools Applies industry leading generative AI solutions to verification work Coaches and mentor others in your areas of expertise Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field OR equivalent experience. Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience. One year of pre-silicon subsystem or IP/block level verification experience. Demonstrated understanding of one or more of the following: fabric interconnects, coherency, Coherent Hub Interface (CHI), Advanced eXtensible Interface (AXI), Advanced Microcontroller Bus Architecture (AMBA), virtualization, security, interrupts, PCIe, CXL, protocol bridges or other complex IP/blocks or subsystems. Understanding of IP verification from definition to silicon, including writing IP/block or subsystem level test plans, developing tests, debugging failures and coverage signoff. Experience creating, maintaining, or integrating test benches, checkers and stimulus using Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), and optionally Python based post-processing checking. Aptitude for writing scripts/software with industry standard languages like Python. Experience applying generative AI to day-to-day tasks.