1000X Faster Chip Design
We build GPU accelerated tools for chip designers. Our Electronic Design Automation (EDA) tools offer 1000x runtime improvements without degrading the quality of the output, thus achieving faster time to tapeout.
Total raised
$5.0M
Last stage
Seed
Investors
William Salcedo
CEO at Partcl. Previously at Nvidia, Stanford, and Cornell. I taped-out two chips from scratch as an undergrad and developed one of the earliest chips designed by LLMs. My research at Stanford included using AI techniques to verify circuits.
LinkedIn
Vamshi Balanaga
CTO at Partcl. Previously built embedded ML models at Apple, laser weeding robots at Carbon Robotics, and warehouse automation robots at Fulfil Solutions. Built and launched multiple rockets while running the avionics team at Space Enterprise at Berkeley, Stanford EECS PhD (dropout), UC Berkeley Physics.
LinkedInWilliam Salcedo
CEO at Partcl. Previously at Nvidia, Stanford, and Cornell. I taped-out two chips from scratch as an undergrad and developed one of the earliest chips designed by LLMs. My research at Stanford included using AI techniques to verify circuits.
No applications, no recruiter spam. Just the intro.
A few questions to make sure this role is the right shape for you. Two minutes.
I write the intro, send it to the founder, and handle the back-and-forth.
If they’re a yes, I book the chat. You show up — that’s the whole job-hunt.
