About the role
Partcl is ending the hardware lottery.
We are developing the next generation of chip design automation tools with a focus on performance, scalability and productivity. We envision a future where hardware engineers benefit from advances in AI and believe the first place to start is with advanced optimization tools.
We’re looking for engineers who think in terms of intermediate representations and passes — people who can design the data models that physical-design tools run on, not just use them. You should be able to move seamlessly between high-level IR design and low-level performance work, building the infrastructure that lets placement, routing, and timing engines operate at massive scale.
At Partcl, we’re not here to play it safe - we’re here to win. We want people who wake up every day wanting to win too. If you are interested in solving massive-scale problems in physical AI, come join us.
What you will do:
- Design the core intermediate representations that physical-design tools use to reason about chips
- Build compiler-like pipelines that lower, normalize, and transform design data across stages (netlist → floorplan → PnR → sign-off)
- Architect the physical-design data model as a first-class IR, not just a storage format
- Create high-performance loaders, serializers, and transformation passes for LEF/DEF, Liberty, SPEF, GDS
- Develop APIs that make analysis and optimization passes fast to write and reason about
- Own correctness invariants: name resolution, scoping, units, coordinate systems, legalizations, constraints
- Optimize for query latency, cache locality, memory layout, and parallel traversal
