Senior Principal Digital IC Design Engineer
About the role
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact In this role you’ll be a member of the Data Center Engineering business group. Our group owns the digital design of high performance mixed signal ICs used in high speed interconnects in hyperscaler data centers. These chips implement advanced digital signal processing algorithms and protocol processing to meet demanding performance, speed, power and latency
requirements of the interconnects that power the communication in AI clusters. What You Can Expect • Design, develop, implement, verify, and document micro-architecture and RTL for complex power management integrated circuits. • Work closely with system and chip architects to design industrial quality implementations. • Participate in the full design development cycle, end-to-end, from writing micro-architecture docs, RTL coding, specifications of timing, closely work with design verification teams to review test plans and execution of test, ability to bring up block tests on silicon during lab testing, and maintenance of designed blocks and reusable IPs. • Produce comprehensive block uArchitecture and register Specs. • Schedule detailed reviews with cross-functional teams Evaluate and participate in improving design and verification methodologies. • Supervise or mentor other digital design engineers.
What We're Looking For • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 12+ years of related professional experience. • Master’s degree in Electrical Engineering or related fields with 10+ years of experience. or PhD in EE or ECE or related fields with 5+ years of experience. • Extensive experience in Verilog/SystemVerilog, Synthesis, STA, low power design, Spyglass and Quality checks of the implemented RTL for LINT, CDC. • Hands on experience in scripting language such as Perl/Python. • Proven track record of delivering production-quality designs on aggressive development schedules. • Domain expertise in 802.3 standards and Serdes design is a plus. • Background in Digital Signal Processing, Error Correction codes and physical layer protocols through hands on prior experience is a plus. Expected Base Pay Range (USD) 182,360 - 273,200, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience,