About the role
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Principal Analog Design Engineer with Marvell, you’ll be a lead member of the Central Engineering business group. Central Engineering organization provides most advanced and key analog IPs to all businesses within Marvell: including Data Center, Networking, Connectivity. You’ll be part of a key analog team that makes an outsized impact to the technological arc of innovation in the field of High Speed SerDes Links. What You Can Expect Seeking a Mixed Signal lead to be part of a key team designing highly sophisticated electrical/optical wireline transceiver/SerDes for datacenter connectivity.
Responsibilities would span architectural investigations and implementation for circuits such as PLL, DLL, ADC, CTLE, regulators, amplifiers, TX, RX, CDRs etc. to meet key performance targets and performing design verification using industry standard tools such as SPICE, Spectre, MATLAB etc. As a Lead Analog circuit design engineer, you will be collaborating with system architects and a global team of circuit and physical designers to build best-in-class electrical/optical serial links for AI driven datacenter connectivity solutions. Your work would swing between research and development geared towards circuits at bleeding edge of technology and data rates to hands-on (‘roll-up-the sleeve’) design of circuits for advanced wireline links.
What We're Looking For Completed a MS or PhD in Electrical Engineering with 5-10 years of related experience. Expertise in one or more of the following focus areas of analog design: ADC/DACs, Front-Ends, CTLE, PLL, Timing circuits, CDRs, SerDes. Ability to collaborate with various other design and functional teams: Layout/ Physical design, System architecture, Digital design and Validation for the successful development, release and support of complex mixed signal IPs Strong knowledge on the deep sub-micron CMOS technologies. Keen eye for analog layout in latest deep submicron technologies and supervision of the same to get the key performance for high-speed design Excellent problem solving and analytical skills to take on circuit design challenges. Excellent debug skills to drive test plans and support validation for full cycle development of IPs and products Expected Base Pay Range (USD) 174,530 - 261,400, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience,