About the role
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. This is an existing vacancy. Your Team, Your Impact As a Digital IC Design Senior Principal Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a digital team of about eight people making a big impact on this organization, working on ultra-dense and performance Static Random Access Memory (SRAM) memory compilers. This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates. What You Can Expect As a Senior Principal Design Engineer, you will contribute to chip architectures and lead micro-architecture and RTL development and HW/SW co-design efforts working across multi-functional teams, in developing state-of-the-art designs for custom AI/HPC Hyperscaler customer needs. Additional
responsibilities will include, but not be limited to: Investigate, scope and plan new AI/HPC SOC programs Define ASIC and/or block architecture, micro-architecture and register specification. Participate and drive specification writeup Conduct detailed architectural and/or design requirement reviews with customers, cross-functional teams, IP Vendors Lead and execute the implementation of a specification based on RTL coding techniques and best practices Work with the physical design teams, reviewing and providing guidance in floorplanning, power analysis, synthesis and timing signoff. Work with the Verification team on pre-silicon verification tasks such as reviewing the verification test plans, coverage analysis, full-chip simulation, performance analysis and debug Help develop and/or evaluate design and verification methodologies and participate in improving existing ones Provide mentorship to the more junior team members