About the role
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Compute and Custom Solutions has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast-growing product lines, Marvell technology is powering the next-generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. What You Can Expect Solid knowledge and expertise in defining and developing verification testbench architecture and components. Ability to understand design architecture and design implementation specifications to create verification test plans and drive complete verification assignment. Good knowledge of SoC architecture and experience with Ethernet Protocol Expertise in UVM methodology Programming skills in System Verilog, C, C++ Scripting skills in Perl, Python or Tcl Strong debugging skills Strong mentoring skills Strong cross-functional experience and communication skills
What We're Looking For Have a Bachelor’s or Master’s in Electronics Engineering with 13+ years of relevant experience in the Ethernet domain. Strong verification capabilities and understanding of the complete verification cycle. Independently own verification of block or subsystem. Strong record of owning and driving the verification projects with complex scope. Identifies and proposes innovative solutions to enhance the verification cycle. Participates in debugging within the verification teams, regular interactions with Design teams, regular sync-up meetings. Strong SV-UVM expertise. High-speed Ethernet experience is preferred. Additional